May 28, 2024
Vertical MoS2 transistors with sub-1-nm gate lengths – Nature

Vertical MoS2 transistors with sub-1-nm gate lengths – Nature

  • Liu, Y. et al. Promises and prospects of two-dimensional transistors. Nature 591, 43–53 (2021).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Chhowalla, M., Jena, D. & Zhang, H. Two-dimensional semiconductors for transistors. Nat. Rev. Mater. 1, 16052 (2016).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Akinwande, D. et al. Graphene and two-dimensional materials for silicon technology. Nature 573, 507–518 (2019).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-layer MoS2 transistors. Nat. Nanotechnol. 6, 147–150 (2011).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Desai, S. B. et al. MoS2 transistors with 1-nanometer gate lengths. Science 354, 99–102 (2016).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Moore, G. E. Cramming more components onto integrated circuits. Proc. IEEE 86, 82–85 (1998).

    Article 

    Google Scholar
     

  • Chau, R., Doyle, B., Datta, S., Kavalieros, J. & Zhang, K. Integrated nanoelectronics for the future. Nat. Mater. 6, 810–812 (2007).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Lundstrom, M. Moore’s law forever? Science 299, 210–211 (2003).

    CAS 
    Article 

    Google Scholar
     

  • Migita, S., Morita, Y., Matsukawa, T., Masahara, M. & Ota, H. Experimental demonstration of ultrashort-channel (3 nm) junctionless FETs utilizing atomically sharp V-grooves on SOI. IEEE Trans. Nanotechnol. 13, 208–215 (2014).

  • Novoselov, K. S. et al. Electric field effect in atomically thin carbon films. Science 306, 666–669 (2004).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Deng, N. et al. Black phosphorus junctions and their electrical and optoelectronic applications. J. Semicond. 42, 081001 (2021).

  • Kim, K. S. et al. Large-scale pattern growth of graphene films for stretchable transparent electrodes. Nature 457, 706–710 (2009).

  • Lee, S., Sohn, J., Jiang, Z., Chen, H.-Y. & Wong, H.-S. P. Metal oxide-resistive memory using graphene-edge electrodes. Nat. Commun. 6, 8407 (2015).

  • Sohn, J., Lee, S., Jiang, Z., Chen, H. & Wong, H. P. Atomically thin graphene plane electrode for 3D RRAM. In 2014 IEEE International Electron Devices Meeting (IEDM) 5.3.1–5.3.4 (IEEE, 2014).

  • Wu, F. et al. A 10 nm short channel MoS2 transistor without the resolution requirement of photolithography. Adv. Electron. Mater. 7, 2100543 (2021).

  • Yoon, Y., Ganapathi, K. & Salahuddin, S. How good can monolayer MoS2 transistors be? Nano Lett. 11, 3768–3773 (2011).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Dunlap, W. C. & Watters, R. L. Direct measurement of the dielectric constants of silicon and germanium. Phys. Rev. 92, 1396–1397 (1953).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Xie, L. et al. Graphene-contacted ultrashort channel monolayer MoS2 transistors. Adv. Mater. 29, 1702522 (2017).

    Article 

    Google Scholar
     

  • Liu, C. et al. Two-dimensional materials for next-generation computing technologies. Nat. Nanotechnol. 15, 545–557 (2020).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Yu, Z. et al. Realization of room-temperature phonon-limited carrier transport in monolayer MoS2 by dielectric and carrier screening. Adv. Mater. 28, 547–552 (2016).

    CAS 
    Article 

    Google Scholar
     

  • Tseng, A. A., Kuan, C., Chen, C. D. & Ma, K. J. Electron beam lithography in nanoscale fabrication: recent development. IEEE Trans. Electron. Packag. Manuf. 26, 141–149 (2003).

    CAS 
    Article 

    Google Scholar
     

  • Sinha, S., Cline, B., Yeric, G., Chandra, V. & Cao, Y. Design benchmarking to 7 nm with FinFET predictive technology models. In Proc. 2012 ACM/IEEE International Sympposium on Low Power Electrons and Design 15–20 (Association for Computing Machinery, 2012).

  • Suzuki, K., Tanaka, T., Tosaka, Y., Horie, H. & Arimoto, Y. Scaling theory for double-gate SOI MOSFET’s. IEEE Trans. Electron Devices 40, 2326–2329 (1993).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Xuejue, H. et al. Sub 50-nm FinFET: PMOS.In International Electron Devices Meeting (IEDM) Technical Digest Paper 67–70 (IEEE, 1999).

  • Yang-Kyu, C. et al. Sub-20nm CMOS FinFET technologies. In International Electron Devices Meeting (IEDM) Technical Digest Paper 19.11.11–19.11.14 (IEEE, 2001).

  • Bin, Y. et al. FinFET scaling to 10 nm gate length. In International Electron Devices Meeting (IEDM) Technical Digest Paper 10.2.1-10.2.4 (IEEE, 2002).

  • Fu-Liang, Y. et al. 5nm-gate nanowire FinFET. In Proc. Symposium on VLSI Technology, Digest of Technical Papers 196–197 (IEEE, 2004).

  • Lee, H. et al. Sub-5nm all-around gate FinFET for ultimate scaling. In Proc. Symposium on VLSI Technology, Digest of Technical Papers 58–59 (IEEE, 2006).

  • Yeo, K. H. et al. Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires. In International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2006).

  • Loubet, N. et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In Symposium on VLSI Technology T230-T231 (IEEE, 2017).

  • Franklin, A. D. et al. Sub-10 nm carbon nanotube transistor. Nano Lett. 12, 758–762 (2012).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Cao, Q., Tersoff, J., Farmer, D. B., Zhu, Y. & Han, S.-J. Carbon nanotube transistors scaled to a 40-nanometer footprint. Science 356, 1369–1372 (2017).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • Qiu, C. et al. Scaling carbon nanotube complementary transistors to 5-nm gate lengths. Science 355, 271–276 (2017).

    ADS 
    CAS 
    Article 

    Google Scholar
     

  • English, C. D., Smithe, K. K. H., Xu, R. L. & Pop, E. Approaching ballistic transport in monolayer MoS2 transistors with self-aligned 10 nm top gates. In International Electron Devices Meeting (IEDM) 5.6.1–5.6.4 (IEEE, 2016).

  • Jiang, J. et al. Ultrashort vertical-channel van der Waals semiconductor transistors. Adv. Sci. 7, 1902964 (2020).

    CAS 
    Article 

    Google Scholar
     

  • Zou, X., Liu, L., Xu, J., Wang, H. & Tang, W.-M. Few-layered MoS2 field-effect transistors with a vertical channel of sub-10 nm. ACS Appl. Mater. Inter. 12, 32943–32950 (2020).

    CAS 
    Article 

    Google Scholar
     

  • International Roadmap for Devices and Systems (IRDS™) 2021 Edition (IEEE, 2021); https://irds.ieee.org/editions/2021

  • Bohr, M. A 30 year retrospective on Dennard’s MOSFET scaling paper. IEEE Solid-State Circuits Soc. Newsl. 12, 11–13 (2007).

    Article 

    Google Scholar
     

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